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MAX2391EGI Rev. A
RELIABILITY REPORT FOR MAX2391EGI PLASTIC ENCAPSULATED DEVICES
February 3, 2004
MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX2391 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information IV. .......Die Information V. ........Quality Assurance Information VI. .......Reliability Evaluation ......Attachments
I. Device Description A. General The MAX2391 fully integrated direct-conversion receiver IC is designed specifically for W-CDMA applications. With the MAX2395, the MAX2391 forms a complete single-mode W-CDMA radio chipset. The MAX2391 provides a complete antenna-to-baseband solution for the 3GPP W-CDMA FDD receiver (2110MHz to 2170MHz, 3.84Mcps), eliminating the use of an off-chip IF SAW filter, as well as external RX LO generation and synthesis. The MAX2391 receiver ICs have over 90dB of dynamic gain control, and a receive sensitivity of -112dBm referred to LNA input. The receiver consists of an ultra-low current low-noise amplifier (LNA) with on-chip output matching and a two-step gain control. The zero-IF demodulator has a differential circuit topology for minimum LO leakage to the receiver's input. The channel selectivity is done completely in the baseband section of the receiver with an on-chip lowpass filter. The AGC section has over 50dB of gain control range. LO quadrature generation is done onchip through a divide-by-2 prescaler. The DC offset cancellation in the I/Q baseband channels is done fully on-chip using a DC servo loop. To quickly correct for large DC offset transients in minimal time, very fast settling time is obtained by optimization of the DC-offset cancellation circuit's time constant. The MAX2391 includes a 3-wire serial bus for PLL programming and for configuring the different receiver modes. It also includes a SHDN pin for full device shutdown. The MAX2391is fabricated using an advanced high-frequency SiGe BiCMOS process. The IC operates from a single +2.7V to +3.3V supply and is housed in a small 28-pin leadless QFN-EP package (5mm x 5mm). B. Absolute Maximum Ratings Item VCC to GND All Other Pins to GND LNA_IN Digital Input Current Digital Output Open-Collector Current Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) 28-Pin QFN Derates above +70C 28-Pin QFN Rating -0.3V to +3.6V -0.3V to (VCC + 0.3V) +15dBm 10mA 1mA -40C to +85C +150C -65C to +160C +300C 1.667W 20.8mW/C
II. Manufacturing Information A. Description/Function: B. Process: C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: W-CDMA Zero-IF Receivers MB20 Bi-CMOS Process 8883 Oregon, USA Korea January, 2003
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: I. Classification of Moisture Sensitivity per JEDEC standard JESD22-A112: 28-Pin QFN Copper Solder Plate Silver-Filled Epoxy Gold (1.0 mil dia.) Epoxy with silica filler # 05-9000-1020 Class UL94-V0
Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 120 x 98 mils Si3N4 (Silicon nitride) Au None 1.2 microns (as drawn) Metal 1, 2 & 3 5.6 microns (as drawn) Metal 4 1.6 microns (as drawn) Metal 1, 2 & 3, 4.2 microns (as drawn) Metal 4 3.4 mil. Octagonal SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Manager, Reliability Operations) Bryan Preeshl (Executive Director of QA) Kenneth Huening (Vice President) B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 150C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 192 x 9823 x 99 x 2 (Chi square value for MTTF upper limit)
Temperature Acceleration factor assuming an activation energy of 0.8eV = 4.90 x 10-9 = 4.90 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability qualification and monitor programs. Maxim also performs weekly Burn-In on samples from production to assure reliability of its processes. The reliability required for lots which receive a burn-in qualification is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on rejects from lots exceeding this level. The attached Burn-In Schematic #06-7084 shows the static circuit used for this test. Maxim also performs 1000 hour life test monitors quarterly for each process. This data is published in the Product Reliability Report (RR-B2A). B. Moisture Resistance Tests Maxim evaluates pressure pot stress from every assembly process during qualification of each new design. Pressure Pot testing must pass a 20% LTPD for acceptance. Additionally, industry standard 85C/85%RH or HAST tests are performed quarterly per device/package family. C. E.S.D. and Latch-Up Testing The WC17-1 die type has been found to have all pins able to withstand a transient pulse of <200V, per MilStd-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 250mA.
Table 1 Reliability Evaluation Test Results MAX2391EGI
TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
Static Life Test (Note 1) Ta = 150C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
99
0
DC Parameters & functionality
77
0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters & functionality 77 0
Note 1: Life Test Data may represent plastic DIP qualification packages. Note 2: Generic package/process data.
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 a. b. Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply p ins (e.g., V , or V SS1 SS2 or V SS3 or V CC1 , or V CC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B Mil Std 883D Method 3015.7 Notice 8
R = 1.5k C = 100pf
TERMINAL D
DOCUMENT I.D. 06-7084
REVISION B
MAXIM
TITLE: BI
Circuit (MAX2391/2392/2393/2396)
PAGE
2
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